Linux 7.3 Expands Support for New RISC-V Extensions

The development of Linux 7.3 incorporates support for discovering and enumerating several recent extensions of the RISC-V architecture, along with improvements in security, memory, performance counters, firmware, and quality of service.

• Linux 7.3 will be able to discover and enumerate RISC-V extensions such as Smcsrind, Zicclsm, Za64rs, and Ssqosid.
• The improvements cover access to registers, unaligned loads, atomic operations, LR/SC sequences, and resource monitoring.
• The RISC-V port also adds changes for Shadow Stack, CPU context switching, and UEFI shutdown and reboot services.

The development of Linux 7.3 adds support for discovering and enumerating several recent extensions of the RISC-V architecture, an instruction platform that aims to broaden the diversity of processors through an open standard. The changes are not limited to identifying new hardware capabilities; they also include adjustments related to security, performance, resource management, and firmware services.

More Extensions to Identify Processor Capabilities

The new support includes the extensions Smcsrind, Sscsrind, Smcntrpmf, Ssccfg, Smcdeleg, Zicclsm, Ziccamoa, Ziccif, Ziccrse, Za64rs, and Ssqosid. Their incorporation allows the kernel to more accurately recognize the features offered by a RISC-V processor, which is important for software to adapt its operation to the available hardware without relying on generic methods.

Smcsrind and Sscsrind are linked to an indirect access mechanism for control and status registers, known as CSR. These registers concentrate essential parameters of the processor and system, so recognizing this capability can facilitate the management of architectures that incorporate a broader or specialized organization of these registers.

Another part of the set relates to counters and their management at different privilege levels. Smcntrpmf adds filtering by privilege mode for cycle and instruction counters, while Ssccfg allows managing delegated hardware performance counters and their configuration states in the contexts provided by the architecture.

Smcdeleg completes this block by defining the delegation of supervisor counters and covering modifications to control and status registers, as well as the behavior of a hardware unit, or hart, at different privilege levels. Together, these extensions provide the operating system with more detailed tools to separate, observe, and manage the activity occurring at each execution level.

Memory, Atomicity, and Instruction Progress

Linux 7.3 also adds support for Zicclsm, an extension that describes the capabilities of the processor and main memory to handle unaligned loads and stores. When this extension is present, certain unaligned accesses can be performed without causing a hardware exception, although the specification warns that its execution may be considerably slow.

The behavior is relevant because unaligned accesses appear in data structures, binary formats, and workloads that do not always organize each element on natural memory boundaries. The explicit recognition of Zicclsm allows the kernel to be aware of this system capability and avoid incorrect assumptions about when an operation should stop or generate an exception.

Ziccamoa focuses on atomic operations and requires that main memory regions with cache and coherence capabilities support the atomic memory operations included in the base extension A. This feature aims to provide a more uniform basis for synchronization mechanisms, where multiple processors or threads must coordinate their accesses without corrupting shared states.

On its part, Ziccif indicates that the main memory supports obtaining instructions with atomicity requirements. Ziccrse points out that this memory guarantees the progress of Load-Reserved/Store-Conditional sequences, known as LR/SC, while Za64rs establishes requirements for the reservation sets used by these instructions, including the guarantee that they are contiguous.

System Resource Security and Management

Among the additional improvements of the RISC-V port is the work on Shadow Stack within control flow integrity mechanisms. This technique maintains a separate structure to protect return addresses and help detect alterations in the expected execution sequence, so its evolution in the core can strengthen defenses against certain control flow attacks.

The development also incorporates support for CPU context switching associated with quality of service tagging. Context switching occurs when the operating system changes the task using a processor, and the handling of these tags seeks to preserve the necessary information to apply differentiated policies among workloads during those changes.

Ssqosid corresponds to the quality of service identifiers for supervisors and is aimed at monitoring resources such as memory bandwidth and cache. For multi-tasking environments, this information can help the operating system observe how resources are distributed and distinguish between the needs of different workloads, although the concrete utility will depend on the hardware and software implementing the extension.

The set is completed with the use of UEFI firmware services to restart and shut down machines. By relying on the services available in the firmware, Linux can have a more coherent way to execute these operations on compatible RISC-V platforms, especially when the system design requires coordination between the kernel, firmware, and the specific machine implementation.

What It Means for the RISC-V Ecosystem

RISC-V uses an open instruction base that can be expanded through standardized extensions, a feature that allows designing processors for specific needs without abandoning a common framework. For Linux, the challenge is to recognize these capabilities, expose them securely, and utilize their guarantees without assuming that all machines offer exactly the same set of features.

The incorporation of these extensions does not mean that every distribution will automatically activate all its advantages on any computer. The benefit will depend on whether the processor declares the corresponding capabilities, whether the firmware configures them correctly, and whether the applications or kernel subsystems know how to take advantage of them when convenient.

Support for unaligned memory, atomicity, and LR/SC sequences can be especially important for software compatibility and for coherence among different RISC-V implementations. In turn, extensions related to counters, privileges, and quality of service offer a more detailed foundation for systems that need to measure performance, isolate workloads, or manage shared resources.

The changes described still belong to the development process of Linux 7.3, so their final form will depend on the evolution of the code and the decisions made before the release.

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